// **************************************************************
// COPYRIGHT(c)2021, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    :axis_conv_rx_40
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  928130120@qq.com
// Data         :  2021/7/8
// Version      :  V 1.0 
// 
//Abstract      :
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
// `include "top_define.v"
// *******************
// *******************
// DESCRIPTION
// *******************
// 40G\u63a5\u6536\u5904\u7684axis\u8de8\u65f6\u949ffifo
// clk 312.5 -> 156.25 or 312.5 -> 630
// axi_data_width 256 -> 256
// TIMESCALE
// ******************* 
module axis_conv_rx_40(
    input  wire [ 9:0]   ram_2p_cfg_register,
    input  wire [11:0]   ram_dp_cfg_register,

	input  wire				m_axis_areset 	,
	input  wire  			m_axis_aclk 	,
		
	input  wire 			m_axis_rtvalid	,
	output wire 			m_axis_rtready	,
	input  wire [63 :0]		m_axis_rtdata 	,
	input  wire [ 7 :0]		m_axis_rtkeep 	,
	input  wire 			m_axis_rtlast 	,
		
	input  wire 			s_axis_aclk 	,
	input  wire 			s_axis_areset 	,

	output wire  			s_axis_rtvalid 	,
	input  wire 			s_axis_rtready 	,
	output wire  [255:0]	s_axis_rtdata  	,
	output wire  [ 31:0]	s_axis_rtkeep  	,
	output wire  			s_axis_rtlast  	
	);
//*******************
//DEFINE PARAMETER
//*******************
//Parameter(s) 

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS

//WIRES
wire  		  m_axis_rtvalid_out;
wire 		  m_axis_rtready_in ;
wire  [255:0] m_axis_rtdata_out ;
wire  [ 31:0] m_axis_rtkeep_out ;
wire  		  m_axis_rtlast_out ;
//*********************
//INSTANTCE MODULE
//*********************
//----------------------------------------------------
//               \u6e90\u65f6\u949f\u57df\u6570\u636e\u4f4d\u5bbd\u8f6c\u6362\uff0864-256\uff09
//----------------------------------------------------
axis_clock_converter_nb64_256  U_axis_clock_converter_nb64_256(
    
    .ram_2p_cfg_register(ram_2p_cfg_register),

    .m_axis_rst_n                 (m_axis_areset       ),
    .m_axis_clk                   (m_axis_aclk         ),
    
    .m_axis_rtvalid_in            (m_axis_rtvalid      ),
    .m_axis_rtready_out           (m_axis_rtready      ),
    .m_axis_rtdata_in             (m_axis_rtdata       ),
    .m_axis_rtkeep_in             (m_axis_rtkeep       ),
    .m_axis_rtlast_in             (m_axis_rtlast       ),
    
    .m_axis_rtvalid_out           (m_axis_rtvalid_out   ),
    .m_axis_rtready_in            (m_axis_rtready_in    ),
    .m_axis_rtdata_out            (m_axis_rtdata_out    ),
    .m_axis_rtkeep_out            (m_axis_rtkeep_out    ),
    .m_axis_rtlast_out            (m_axis_rtlast_out    )
);
//----------------------------------------------------
//          \u6e90\u65f6\u949f\u57df\u5230\u76ee\u7684\u65f6\u949f\u57df\uff08\u8de8\u65f6\u949f\u57df \u6570\u636e256\uff09
//----------------------------------------------------
axis_conv_rx U_axis_conv_rx(
    .ram_dp_cfg_register(ram_dp_cfg_register),

    .m_axis_areset            (m_axis_areset     ),
    .m_axis_aclk              (m_axis_aclk       ),
    
    .m_axis_rtvalid           (m_axis_rtvalid_out),
    .m_axis_rtdata            (m_axis_rtdata_out ),
    .m_axis_rtkeep            (m_axis_rtkeep_out ),
    .m_axis_rtlast            (m_axis_rtlast_out ),
    .m_axis_rtready           (m_axis_rtready_in ),
    
    .s_axis_aclk              (s_axis_aclk       ),
    .s_axis_areset            (s_axis_areset     ),
    
    .s_axis_rtvalid           (s_axis_rtvalid    ),
    .s_axis_rtready           (s_axis_rtready    ),
    .s_axis_rtdata            (s_axis_rtdata     ),
    .s_axis_rtkeep            (s_axis_rtkeep     ),
    .s_axis_rtlast            (s_axis_rtlast     )
    );
//sim \u8de8\u65f6\u949f\u57df\u6570\u636e\u5bf9\u6bd4
// integer f_m;
// integer f_s;
// integer f_m_last;
// integer f_s_last;

// initial begin
//         f_m = $fopen("m_recieve_data_256.txt");
//         f_s = $fopen("s_recieve_data_256.txt");
//         f_m_last = $fopen("m_last_data_256.txt");
//         f_s_last = $fopen("s_last_data_256.txt");
// end

// always@(posedge m_axis_aclk) begin
//     if(m_axis_rtvalid_out) begin
//         $fwrite(f_m,"%h\n",m_axis_rtdata_out);
//     end
//     else if(m_axis_rtlast_out && m_axis_rtvalid_out)begin
//         $fwrite(f_m_last,"%h\n",m_axis_rtdata_out);
//     end
// end
// always@(posedge s_axis_aclk) begin
//     if(s_axis_rtvalid) begin
//         $fwrite(f_s,"%h\n",s_axis_rtdata);
//     end
//     else if(s_axis_rtlast && s_axis_rtvalid)begin
//         $fwrite(f_s_last,"%h\n",s_axis_rtdata);
//     end
// end

endmodule 
